The power required to increase computing performance, especially in embedded or sensor systems has become a serious constraint and is restricting the potential of future systems.
Technologists from the Defense Advanced Research Projects Agency are looking for an ambitious answer to the problem and will next month detail a new program it expects will develop power technologies that could bolster system power output from today's 1 GFLOPS/watt to 75 GFLOPS/watt.
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"Examples show we need at least 50 GFLOPS/w, and requirements of at least 75 GFLOPS/w can be confidently anticipated. Current systems provide in the order of 1 GFLOPS/w and industry trends will provide power efficiencies that are well short of required performance," DARPA stated.
The goal of the program, called Power Efficiency Revolution For Embedded Computing Technologies or PERFECT, is to take a revolutionary approach to processing power efficiency. From DARPA: "This approach includes near threshold voltage operation, massive heterogeneous processing concurrency, and novel architectural developments combined with techniques to effectively utilize the resulting concurrency and tolerate the resulting increased rate of soft errors. The PERFECT program will leverage anticipated industry fabrication geometry advances to 7 nm. Research and development will specifically address embedded systems processing power efficiencies and performance, and are not concerned with developments that focus on exascale processing issues. No operational hardware is to be built in this program, instead a simulation capability will be developed that will measure and demonstrate progress."
In the past, computing systems could rely on increasing computing performance with each processor generation. Following Moore's Law, each generation brought with it double the number of transistors. And according to Dennard's Scaling, clock speed could increase 40% each generation without increasing power density. This allowed increased performance without the penalty of increased power, DAPRA stated.
"That expected increase in processing performance is at an end," said DARPA Director Regina Dugan in a statement. "Clock speeds are being limited by power constraints. Power efficiency has become the Achilles Heel of increased computational capability."
DARPA said PERFECT system development will address five areas including:
Architecture: to address hardware and software power efficiency innovation and development. Example areas anticipated for development include near threshold voltage operation, heterogeneous massive concurrent architectural approaches, and novel hardware architectural approaches such as new memory hierarchies, application-specialized cores, and data movement minimizing techniques. At the software level, the goal is to develop technologies and techniques that tolerate and exploit new hardware capabilities and overcome the associated limitations. This specifically will include addressing concurrency and reliability.
Concurrency : This element will address the hardware and software to support high levels of concurrency - thousands to millions of concurrent execution streams. Hardware efforts in this area may include processing cores and data stores of varying capabilities and efficiencies and perhaps include automatically synthesized processing elements that are optimized for the embedded platform's workload. Software efforts in this area may include language development or augmentation, compilers, and support software to specify and manage concurrent threads.
Resiliency: Will focus on the issue of soft errors. Such errors are expected to increase for near threshold voltage operation.
Locality: Will focus on minimizing run-time data communication by managing data location and availability. In particular, the memory hierarchy and the software to manage data are included. Languages and language annotations that enable programmer control of data allocation as well as automatic control of data allocation will be investigated.
Algorithms: Software techniques to minimize energy consumption. In addition, algorithmic approaches to enable the tolerance of hardware faults will be investigated, at both the kernel and the system levels.
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