In the ever-growing desire to product smaller, less costly yet more powerful and faster computers and storage devices, researchers today said they are looking at a way to use self-growing fabrics that will let manufacturers build nano-sized high resolution semiconductors and arrays that answer that craving.
Researchers at the Nanoscale Science and Engineering Center (NSEC) at the University of Wisconsin - Madison have come up with a method that uses existing technology to combine the lithography techniques traditionally used to pattern microelectronics with novel self-assembling materials known as block copolymers, researchers said. When combined with a lithographically patterned surface, the block copolymers' long molecular chains spontaneously assemble into the designated arrangements, researchers said.
These Block copolymers can spontaneously form features with dimensions as small as 10 nm and only need one-fourth as much patterning information as traditional materials to form the desired molecular architecture, making the process more efficient, researchers said.
"There's information encoded in the molecules that results in getting certain size and spacing of features with certain desirable properties," said Paul Nealey, director of the NSEC in a release. "Thermodynamic driving forces make the structures more uniform in size and higher density than you can obtain with traditional materials.
"These results have profound implications for advancing the performance and capabilities of lithographic materials and processes beyond current limits," Nealey added.
In its current form, this method is well-suited for designing hard drives and other data-storage devices, which need uniformly patterned templates - exactly the types of arrangements the block copolymers form most readily, researchers said. The technology may also be useful for designing more complex patterns such as microchips, researchers said.
Hitachi and IBM earlier this year announced a research pact to shrink the features on silicon chips. Researchers from the companies said they will try to accelerate the miniaturization of chip circuitry by researching at the atomic level for 32-nanometer and 22-nm semiconductors. Making chip circuits smaller should allow computing devices to deliver power savings and performance gains. It will also make manufacturing more efficient, IBM told the IDG News Service.
Meanwhile researchers at the University of Michigan recently said they had created a low-power microchip that uses 30,000 times less power in sleep mode and 10 times less in active mode than comparable chips now on the market. The Phoenix Processor sets a low-power record and is intended for use in cutting-edge sensor-based devices such as medical implants, environment monitors or surveillance equipment according to researchers. The chip consumes 30 picowatts during sleep mode. A picowatt is one-trillionth of a watt. Theoretically, the energy stored in a watch battery would be enough to run the Phoenix for 263 years.
Other researchers said they have developed a fabrication method to create all-copper connections between computer chips and external circuitry, significantly boosting the speed and amount of data that can be sent throughout a computer. Solder and copper can both tolerate misalignment between two pieces being connected, but copper is more conductive and creates a stronger bond, researchers said Georgia Tech School of Chemical and Biomolecular Engineering researchers.
Layer 8 in a box
Check out these other hot stories: