Heavyweight 3D imagery and complex unmanned aircraft systems are just two applications that beg for the low power, high performance custom integrated circuits the researchers at the Defense Advanced Research Projects Agency are looking to build.
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DARPA this week announced a new program called Circuit Realization At Faster Timescales (CRAFT) that looks to radically alter and shorten the design cycle for custom integrated circuits by a factor of 10. It takes on the order of 2.5 years to design and fabricate a custom integrated circuit design for DoD. DARPA wants to see the CRAFT program get that development down to the neighborhood of 30 weeks.
The CRAFT program also looks to formulate design frameworks that can be readily recast when next-generation fabrication plants come on line; and create a repository so that methods, documentation and intellectual property need not be reinvented with each design and fabrication cycle, DARPA stated.
At the core of the CRAFT program is an unprecedented ability to fabricate customized, technology-specific circuits using the 16 nanometer/14 nm commercial fabrication infrastructure that today produces generic commodity circuits, according to Linton Salmon, a program manager in DARPA’s Microsystems Technology Office.
“A custom integrated circuit designed only to process images from an airborne radar or to analyze sensor data for warfighters on the ground doesn’t need to run a spread sheet or a word processor. Why carry around a heavy bulging Swiss Army knife when all you need is a single Phillips-head screwdriver?” Salmon said in a statement.
Being able to jettison the massive amounts of circuitry dedicated to everyday functions would allow the resulting spare capability to be devoted to crucial functions, Salmon continued. “In the end you would have a top-of-the-line, custom-integrated circuit that does only the job you need and does so much more effectively.”
DARPA said it is currently looking for proposals to reduce the barriers facing design teams by addressing key issues such as the following:
- An integrated circuit design flow that reduces the effort required to design/verify a custom integrated circuit by a factor of 10X
- Increased reuse (DoD and 3rd party IP) and lowered level of manpower and design expertise required to design and verify integrated circuits in leading-edge CMOS technology
- Embedding of design and process complexity into circuit components (macros, sub- circuits, generators, compilers) that are designed/verified once and reused many times
- Methods to quickly and easily port custom integrated circuit designs from one foundry process to another similar foundry/process and/or migrate designs to a more advanced CMOS technology node
- Methods to increase reuse by improving the definition, secure storage, and distribution of key design components such as macros, generators, compilers, IP, and technology information
DARPA also pointed to three barriers to using leading-edge CMOS technology to build custom integrated circuits: 1) lengthy and expensive design, verification, and fabrication cycles; 2) difficulty migrating designs from one foundry process to another; and, 3) lack of reusability in DoD designs.
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