Researchers get $6 million to accelerate multicore chip design

The National Science Foundation (NSF) and Semiconductor Research Corporation (SRC), today funded a $6 million, three year program that will focus on building low-power, high function multicore chips for servers, networking equipment and other key computer systems.

    The idea behind the initiative is to significantly advance state-of-the-art multi-core chip design and architecture, bring about system-level performance improvements and establish innovative research areas critical to future computing, the NSF said.  Specific areas of research for the program include computer-aided design for multi-core systems, such as acceleration of design automation tools via multi-core platforms; interconnect, packaging and circuit techniques for multi-core; and low-power innovations. 

A few of the multicore research projects are expected to include:

• On-chip networks or networks-on-chips (NoCs) support the homogeneous or heterogeneous interconnection of processor cores and various levels of the memory hierarchy to facilitate the movement of large amounts of data in minimal time. Problems of communication latency and throughput, area overhead, design complexity, etc., must be overcome. Research is needed on modeling and evaluating alternative NoC topologies, routing strategies, flow control, coding techniques, router microarchitectures, NoC interfaces, and memory interconnect solutions. Related compiler and dynamic techniques for managing scalable on-chip communication are also needed, according to the NSF

• Research into new parallel programming models, memory models/architectures, and hardware and software primitives that facilitate the programmability of multicores for existing and emerging applications is needed. This includes research into hardware and software transactional memories, scalable and highly concurrent synchronization primitives, and compiler and run-time system software support. Optimizing performance by mixing general purpose cores with special purpose cores for applications such as high-end graphics, signal processing, network processing, etc., is also important, according to the NSF.

• Since multicores are likely to be more useful for heterogeneous structures composed of multiple processor cores, accelerators and 3D structures research is needed on how to design software tailored to hardware structures in support of various applications. This hardware/software co-design effort will require identifying re-usable hardware functions such as application-specific accelerator functions and software partitioning decompositions that support new applications and systems development, the NSF stated.

• Simulation of multicore system-level performance and power as a function of interconnect bandwidth and latency for various architectures and applications are of interest. This also includes detailed simulation of multicore signal integrity and power delivery noise. Research on optical interconnect and 3D interconnect technologies are of interest. This includes the feasibility of optical interconnect with wavelength division multiplexing to provide optical crossbar, router, and high-bandwidth/low-latency resource sharing. The potential of variable pitch 3D interconnect technologies for increased die-to-die communication enabling multicore integration is of interest as are the issues of thermal/performance tradeoffs in this context, the NSF stated.

• Research on hardware and software support for optimizing performance-per-watt and energy-per-instruction, and efficiently managing power and temperature of multicore resources is important. Tool development for power reduction and power analysis is also important, as are other tools aware of the multicore context. Relevant issues can be addressed at various levels of the design hierarchy, e.g., at the device, interconnect, circuit, or architectural level, the NSF said.

"As Moore's Law scaling becomes more difficult, researchers must explore new means to insure continued technological advances in computing," said Sankar Basu, NSF program director.  "CMOS scaling is increasingly limited by the realities imposed by physics, making architectural innovations critical to achieving increased computational performance. Multi-core-based systems promise computational performance enhancements and power reduction for both high- and low- end computing platforms."

The NSF and SRC will put up about $6 million for US universities, who are invited to submit research proposals in key areas.

The NSF this week also said the 200,00  processor core system known as Blue Waters got the green light as the University of Illinois at Urbana-Champaign and its National Center for Supercomputing Applications (NCSA) said it has finalized the contract with IBM to build the world's first sustained petascale computational system.

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