AMD and IBM increase the strain on 65nm chips

Advanced Micro Devices and IBM have added two new forms of strained silicon to their jointly developed 65-nanometer chip-making technology, which should improve the performance and reduce the power consumption of future processors, the companies are expected to announce Tuesday.

AMD and IBM will reveal the latest fruits of their collaborative effort at the International Electron Devices Meeting (IEDM), in Washington, D.C., said Gary Bronner, a distinguished engineer with IBM. The companies developed 65-nanometer manufacturing technology at IBM's wafer fabrication plant (fab) in East Fishkill, N.Y.

Future processors from both companies will use transistors that have been stretched in some ways, or compressed in others, to increase the speed at which electrons travel, said Nick Kepler, vice president of logic technology development at AMD. The new methods build upon strained silicon techniques the companies introduced last year at the IEDM and implemented in chips earlier this year, he said.

For years, chip companies have built faster transistors simply by reducing the size of those transistors, a process known as scaling, every two or so years. However, transistors are now getting so small that other methods beyond simple scaling are required to improve chip performance on the schedule expected by hardware vendors and users.

One of those methods is called strained silicon. When certain materials are laid atop the silicon substrate on which transistors are built, the atoms in those substances align with each other, compressing or stretching the silicon. Positive transistors run better when they have been compressed, while negative transistors benefit from being stretched. IBM and AMD introduced Dual Stress Liner technology last year that allowed both types of strain to exist side-by-side on a chip.

The companies have developed two new methods of straining transistors that build on the Dual Stress Liner (DSL) technique to improve the performance of 65nm processors, said John Pellerin, director of logic technology development at IBM. The label of 65nm manufacturing technology corresponds to the average size of features on the chips, in this case a reduction from the current 90nm generation of chip-making technology.

The first method, known as stress memorization technology, improves the performance of negative transistors by adding a thin film of silicon nitride to a negative transistor, causing the atoms to move, and then removing that film, Pellerin said. The atoms "memorize" their position and stay in place after the film is removed, hence the name, he said.

The second method involves adding silicon germanium to positive transistors, Bronner said. The silicon germanium is essentially grown right next to the transistor gate, compressing that channel. The companies used to consider silicon germanium a difficult material to use in high-volume chip manufacturing, but they became accustomed to the use of the material during their collaboration, he said.

The IDG News Service is a Network World affiliate.