Taking a look at the basics of ASICs

Growth in the demand for bandwidth and advanced functions is outpacing the performance of software routers based solely on Reduced Instruction Set Computing (RISC) processors, making this approach unsuitable for next-generation router design.

Many router designers have begun to supplement or replace RISC processors with full custom Application Specific Integrated Circuits (ASIC).

Basically, ASICs are chips that have been built to act on a particular application. ASICs can consolidate the work of many chips into a single, smaller, faster package, reducing manufacturing and support costs while boosting the speed of the device built with them. ASIC technology is now so advanced that many functions traditionally implemented in software can be migrated to ASICs.

More specifically, ASICs let designers use the power of constantly improving silicon technology to build devices targeted at specific functions, such as routing.

Over the past decade, ASIC technology has seen massive improvements in density and performance driven by the ever smaller processes of the silicon. The latest 0.25-micron ASIC technology supports more than five million gates on a single 150-MHz chip. Ten years ago, 1.5-micron technology could sustain 25-MHz performance. Density was commonly 10,000 to 20,000 gates. Five years ago, 0.6-micron technology could sustain 66-MHz performance and density was commonly 75,000 to 100,000 gates.

A gate is a circuit on the ASIC, and gates can be arranged in a number of ways.

The gate array and number of gates on a chip can determine the ASIC's overall function. Experts predict there could be as many as 10 million gates deployed in computer equipment, and the ASIC industry could be worth some $8 billion by 2005.

Vendors have the choice of customizing all or parts of the gates and the logic it takes to operate them.

ASIC vendors such as IBM offer a basic ASIC library that other vendors can choose from. In the past, basic elements such as memory were standard ASIC fare, but now complex designs - such as Gigabit Ethernet features or support for PCI controllers-or what ASICs vendors call cores, are being added to many ASIC vendor menus.

These technology advances mean that more functions can be moved into hardware, dramatically reducing the number of processing cycles and increasing performance levels as well as functions.

Performance improvements of up to threefold can be achieved through the use of ASICs when compared with the same functions being executed in software.

But when you migrate functions to silicon, there is a trade-off. A fully hard-wired implementation of a router can be inflexible and risky. Standards, particularly as they apply to the WAN edge, are still in a state of flux.

For example, quality-of-service (QoS) mechanisms, such as the IETF's Differentiated Services, are still evolving. New protocols, including Multiprotocol Label Switching and Layer 2 Tunnel Protocol, are just emerging. New IP encapsulation schemes are being proposed.

As a result, it would be ill-advised to hard-wire various frame processing functions into ASICs for quite some time.

A better approach might be a precise blend of RISC and ASIC technology. This approach provides the ultimate flexibility of a RISC processor with the performance, density and cost benefits of a fully hard-wired ASIC solution.

Generic functions, such as buffer management, queue management, QoS scheduling, address lookup and flow classification, can be off-loaded to ASIC silicon with no risk.

Packet-header processing functions, such as Layer 2 and Layer 3 packet-header parsing and modifications, along with QoS control, statistics harvesting and other "likely-to-change" functions, can be partitioned onto RISC processors for flexibility.

Deciding how many packet- header processing functions should be hard-wired and how many should be downloaded in firmware to a programmable RISC processor will require different trade-offs.

The correct blend ultimately depends on the market segment being targeted by the designers of a particular switch or router.

Software-only implementations of switches and routers are flexible but do not have adequate performance, particularly when it comes to implementing advanced features such as QoS. Hard-wired ASIC implementations will provide very high performance but will not provide the flexibility so important to the WAN edge.

For new network gear, it's 'IBM Inside'
IBM ASICs are powering gear from Nexabit, Xylan and others. Network World, 11/30/98.

Blue Logic overview
From IBM Microelectronics

IBM’s Blue Logic Strategy
Interview with Chris King, director of worldwide marketing and field engineering for IBM Microelectronics, from MicroNews.

The fabless phenomenon
"Fabless semi" firms are building net functions into silicon, paving the way for high-powered, low-cost network gear. Network World, 3/2/98.

Avici offers glimpse intoits really big router
Company's ASIC-based Terabit Switch Router aimed at bulking up the Internet backbone
Network World, 1/12/98.

Lawler and Melden are co-founders of Redstone Communications, a start-up specializing in packet-switched network devices. They can be reached at clawler@ redstonecom.com and kmelden@ redstonecom.com.