HyperTransport boosts bus speeds

HyperTransport is a new, high-speed bus architecture that reduces data bottlenecks and boosts the performance of communications equipment, including PCs, workstations, servers, Internet routers, optical switches, networks, central office equipment and cellular base stations.

Now in the standards review process, HyperTransport is a scalable, point-to-point interconnection technology that provides a high-speed, high-performance link for embedded applications. This universal connection reduces the number of buses within a system and enables chips in any PC, networking or communications device to communicate with other devices up to 24 times faster than existing technologies.

HyperTransport is a scalable architecture that provides more than an order-of-magnitude increase in bus transaction throughput over existing I/O bus technologies, such as PCI, PCI-X and AGP.

Legacy I/O bus architectures are widely used in embedded systems because they are inexpensive and easily implemented using established software and hardware standards. Unfortunately, these buses top out at around 66 MHz. But today's processors run at clock frequencies of 500 MHz to more than 1 GHz, with faster ones coming. HyperTransport I/O bus architecture can scale from narrow configurations with relatively low-speed (200-MHz) clock rates to upwards of 32-bit wide, high-speed (800-MHz and up) clock rates.

With HyperTransport, standard bus widths of 2, 4, 8, 16 and 32 bits can be used to fit the I/O bus characteristics to specific applications. Its inherent flexibility includes asymmetric bus widths to support different upstream and downstream bandwidth needs. A 16-bit HyperTransport I/O bus, for example, can deliver 25.6G bit/sec bandwidth capable of supporting two OC-192 SONET bit streams or two 10G bit/sec Ethernet links.

HyperTransport is backward-compatible with the widely deployed PCI externally visible bus standard. This means already-paid-for PCI software code need not be rewritten - an economic advantage in addition to getting a much faster interface.

One option for getting more bandwidth is to graduate to PCI-X, which operates at 133 MHz. But PCI-X is limited in that only one peripheral device can be plugged in (compared with four with traditional PCI). HyperTransport, on the other hand, can support 31 devices. With a switch it can support even more devices by creating huge HyperTransport fabric (tunnels that act as I/O building blocks) while keeping both systems and hardware costs relatively flat.

Finally, HyperTransport has the potential benefit of a low implementation cost, in addition to its flexibility, scalability and very high bandwidth. Because it is part of the processor roadmap for chip giant AMD's desktop PCs and server systems, HyperTransport will take advantage of economies of scale.

HyperTransport I/O bus architecture can provide the bandwidth for next-generation PCs, servers and communications systems. A multivendor standard that is easily implemented, it will offer a broad selection of bus widths and speeds that can match the power, space and cost requirements of a wide array of embedded systems - from low-cost desktop workstations to digital consumer applications, communications and networking equipment.

Robinson is technical evangelist at API NetWorks. He can be reached at peter.robinson@api-networks.com.