Network performance depends on a switch's forwarding rate and packet loss rate. Latency, congestion and head-of-line (HOL) blocking can slow things down, while quality-of-service (QoS) capabilities can improve network efficiency. This primer can help you understand how these factors are measured and what impact they'll have on your network.
Forwarding rate and packet loss rate
The classic throughput test defined in RFC1944 determines the maximum forwarding rate at which a device loses zero packets. Once a packet is dropped at a given speed, testing at that speed stops and the rate is adjusted to find the maximum loss-free throughput rate. This test is more stressful and exacting than a simple forwarding rate test, which does not penalize a switch that drops an occasional packet at all offered loads.Latency
Lots of attention is paid to switch latency, particularly with regard to real-time applications. In reality, switch latency is much less of a consideration today than it was with the Ethernet hub-router-FDDI campus network equipment of the recent past. Modern Layer 2 switches generally use distributed architectures implemented with ASICs to reduce store and forward latencies into the 5 to 50 microseconds range. Switch latency in this range has been shown to be a small contributor to user-perceived response times. In fact, for virtually all Ethernet switching, the biggest contributor to network latency is the serialization time or packet transmission time (1.2 milliseconds per switch hop for a 1,518-byte packet at 10M bit/sec; 120 micro-seconds at 100M bit/sec; and 12 microseconds at 1G bit/sec). If a packet is stored several times between source and destination, a serialization delay is incurred for every hop along the path.Congestion
Congestion occurs when traffic from multiple input ports converges on and oversubscribes an output port or when heavy traffic loads from a high-speed port are switched to a lower speed port. The congested port's buffers fill and eventually overflow, causing packet loss. One of the arts of switch design is to come up with the right combination of buffer capacity and buffer/queue management to meet application requirements. While it is not possible to specify exactly what the ideal results are for a congestion test, some fairly standard heuristics can be applied. One rule of thumb is that maximum burst sizes should be adequate for multiple clients to simultaneously upload data to a server. One individual high-performance system can generate bursts of approximately 40 1,518-byte packets. A fairly robust design from this perspective would allow three to five bursts to coincide on a server or backbone switch port without packet loss. Another rule of thumb is based on calculating the time it would take for a full buffer to be drained as a worst case of the delay associated with congestion. For example, in the 3:1 congestion test, a switch that accommodates a burst of 150 packets before loss has an allocated port buffer capacity of approximately 100 packets. One hundred maximum-sized packets would drain from the buffer in 1.2 milliseconds at Gigabit Ethernet speeds and in 12 milliseconds at Fast Ethernet speeds. From this perspective, Gigabit Ethernet buffers can be larger than Fast Ethernet buffers without introducing excessive potential delay.Head-of-line blocking
If a switch displays HOL blocking, packets are FIFO queued in a buffer at the input port or within the switch fabric. A packet destined for a noncon-gested output port can be forwarded only after all packets ahead of it in the queue are forwarded, resulting in buffer overflow and packet loss for traffic streams forwarded over uncongested and congested ports. Conversely, a switch without HOL blocking will not drop any packets destined to uncongested ports, no matter what the congestion is on other ports. HOL blocking is a performance-limiting characteristic of a class of input buffered switches that includes cross-point matrix switches. Computer simulations have shown that HOL can restrict the switch's average forwarding performance to approximately 60% of the switch fabric capacity. How-ever, a number of design strategies can reduce or eliminate HOL effects in matrix switches, and the majority of vendors employ them successfully enough that today's switches don't usually have problems with HOL blocking.QoS capabilities
Another major area of differentiation, at least until standards solidify, is how vendors deliver QoS capabilities. Simple FIFO queuing can have serious shortcomings in real networks where all traffic is not generated by a homogeneous set of delay-insensitive applications. If the vision of a converged LAN, carrying voice, video and traditional data traffic, is to be realized, switched infrastructures will need to manipulate multiple logical queues to minimize impact on varied network applications. Testing these QoS capabilities will require development of a new suite of tests that determine how effective buffer and queue management schemes are at controlling buffer delays and packet loss rates. The congestion and the HOL blocking tests performed as part of this evaluation are examples of some modest steps in the direction of benchmarks that help address some questions that need to be answered before leaping into a new world of QoS-enabled LANs. RELATED LINKS Review: Backbone switchesWe put several through their paces.
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RFC 1944
Benchmarking methodology for network interconnect devices.
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