DARPA tackling reusable, modular chipset technology

DARPA says today’s leading edge electronic designs are complex, expensive, and often involve teams spread across the globe


Is it possible to develop chip technology that combines the high-performance characteristics of ASICS with the speedy, low-cost features of printed circuit boards?

Scientists at the Defense Advanced Research Projects Agency this week said they were looking for information on how to build interface standards that would enable modular design and practical circuit blocks that could be reused to greatly shorten electronics development time and cost.

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One technique for addressing rising cost and complexity has been the use of a modular design flow that subdivides a system into functional circuit blocks, called IP blocks, DARPA stated. “IP block refers to intellectual property captured in a pre-designed functional circuit block. Examples of IP blocks include, but are not limited to, timing circuits, filters, waveform generators, embedded processors, data converters, amplifiers, fast Fourier transforms, serializer-deserializers and memory,” the agency stated.

DARPA calls the potential framework CHIPS and suggested that one possible developmental path would be to instantiate IP blocks as chiplets or functional dies, that can be assembled onto modular integration platforms. These chiplets would leverage standard layouts and interfaces to seamlessly link to other chiplets.

“It is anticipated that the use of standard interfaces will enable access to a large catalog of commercial and government off-the-shelf IP blocks, reuse of existing IP blocks, and heterogeneous integration of blocks in other technologies and nodes. It is further anticipated that a fully implemented CHIPS ecosystem will substantially reduce the time and cost to realize new circuit functions,” DARPA stated.

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“Today’s leading edge electronic designs are complex, expensive, and often involve teams spread across the globe; factors that have driven drastic growth in non-recurring engineering costs. Additionally, the monolithic nature of these designs means that any change to a portion of the chip requires a re-spin of the entire chip. The high cost notwithstanding, these application specific integrated circuits (ASICs) are unrivaled in their performance. Many large commercial designers can spread these costs over the large volumes of consumer products, but for low-volume customers like the DoD, start-up companies, and academia, these mounting costs have restricted access to the latest device technologies,” DARPA stated.

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Some of the questions DARPA is looking for answers to include:

  • What standards should be considered? What are the best ways to compare between different standards?
  • Do new standards need to be developed, or how can existing standards be leveraged effectively?
  • How would compliance with selected interface standards be evaluated?
  • What IP blocks should be available to the community, and what electronic and physical formats are preferred? What else needs to be defined to use commercial or third-party IP blocks? Can this process be automated?
  • What is the optimal IP block granularity? Are there specific blocks that benefit from heterogeneity? What are the trade-offs (e.g., scalability vs. performance)
  • What factors affect the minimum, maximum, and optimal chiplet size? What is the optimal spacing between chiplets? What is the minimum interconnect pitch required?
  • How much time and cost savings could be expected for designs with access to the CHIPS ecosystem?

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Copyright © 2016 IDG Communications, Inc.

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