To put it simply, the Cisco QuantumFlow Processor (QFP) is everything on a chip.
Several weeks ago I wrote a couple blogs on the Cisco ASR 1000-series routers: one blog on the hardware architecture of the ASR 1000-series and a blog on Cisco IOS XE. Before finishing my little series on the ASR 1000-series I thought it would be good to review the Cisco QuantumFlow Processor (QFP), the engine in the ASR 1000-series.
One disclaimer before I begin: I do not pretend to be, nor do I every plan to be, an expert on CPU design. However, I have been working with computers, IT, and networking for about 15 years now, so I can understand and relate the concepts. However, design a CPU like an Intel PhD engineer, I cannot.
To be put simply, the Cisco QuantumFlow Processor (QFP) is everything on a chip. Gone are the days where you bought a large router – let’s pick on the 7200-series – and also had to buy daughter cards or rely on the main CPU for encryption, firewalls, network management, QoS, etc. Quoting from Cisco.com:
“General-purpose processors enabled flexible network services and rapid feature development but lacked traffic prioritization mechanisms and suffered from slow forwarding performance”.
Instead, the QFP puts all of those services – Layer 2-7 – on the CPU itself. The QFP does this by using a flexible and programmable CPU design which utilizes 40 4-way-threaded (160 total) CPU cores called Packet Processing Engines (PPE). Incoming packets are distributed among the 40 engines. One of the 4 threads in each engine handles a packet. With 160 threads, the QFP can handle complex layer 2-7 operations in the CPU at wire-speed, not on daughter cards. This massive amount of parallel processing reduces any requirements for external service blades inside the router. All processing is performed on the QFP. Furthermore, through proper software design, there is no serialization of every L2-L7 service on each packet. The QFP knows to only apply appropriate services to each packet, reducing latency and CPU utilization. This allows you to run a variety of enhanced services right on the QFP: After the packet is handled by a PPE it is sent to the Traffic Manager where it is queued for transmission out an interface. The Traffic Manager supports over 100,000 hierarchial queues to ensure critical traffic (Voice and Video) get preferential treatment through the scheduler. The entire flow of a packet through the QFP is done in four steps:
This single-CPU-for-everything design is made possible by the QFP’s flexible programming design using ANSI-C code. Instead of difficult machine-level coding, new features can be added to the QFP using rapid C-coding with industry-standard programming tools. The new hardware accelerated service then can be added with a software upgrade to the router. This should mean Cisco can deliver some great new hardware supported feature in the future with just an IOS XE upgrade. The QFP itself is part of the ASR Embedded Service Processor (ESP):
Cisco also notes that the QFP may be used in the future as the main CPU on linecard for high-end devices (CRS-1, GSR, Nexus, etc.)
This family of the QFP can support up to 100Gbps of external, bidirectional (to the chip) bandwidth across multiple interfaces. Each PPE can execute 1200 millions of instructions per second (MIPS), translating into packet latency in as little as 10’s of microseconds with features enabled (1,200,000,000 * 40 PPEs per QFP = 48,000,000,000 instructions per second). Future revisions of the QFP will undoubtedly support higher bandwidths. Overall, the QFP is a very impressive piece of hardware. I am not going to miss buying daughter cards in routers to do a CPU intensive task. Nor will I miss worrying about adding a feature – like NBAR – that could melt the router down. I am looking forward to getting our ASRs installed next month.
Cisco QuantumFlow Processor (QFP) “Marketing” Video:
