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Power cuts key for Intel at 65 nanometers

Aug 30, 20044 mins
Computers and PeripheralsNetwork Security

Intel’s 65-nanometer process technology will not be very different from its 90-nanometer process technology, which should help make for a smoother transition between the two manufacturing techniques in 2005, according to a briefing from an Intel manufacturing executive last week.

Intel’s 65-nanometer process technology will not be very different from its 90-nanometer process technology, which should help make for a smoother transition between the two manufacturing techniques in 2005, according to a briefing from an Intel manufacturing executive last week.

The company will continue to use its strained silicon technique and low-k dielectric material on the new 65-nanometer process technology, but will add an eighth metal interconnect layer and introduce power-saving sleep transistors into some chips built with the new manufacturing technology, said Mark Bohr, a senior Intel fellow and director of process architecture and integration.

Every two to three years, the semiconductor industry shrinks the structures on its chips to pack more and more transistors onto a silicon die. Most companies have already introduced 90-nanometer chips this year. A nanometer is one-billionth of a meter, and the 90-nanometer designation refers to the average size of the structures on a chip.

A process-technology shrink is a painstaking exercise making sure these complex structures will be just as reliable as the previous generation of products after having shrunk in size. The transition to the 90-nanometer process generation has been difficult for some companies as power leakage has become more of a problem at this level than in previous process generations.

“We’ve all gotten religion on power,” Bohr said. “We’ve placed an ever greater emphasis on power reduction techniques and ideas (at 65 nanometers).”

Intel is keeping the same strained silicon technique used to make its 90-nanometer chips, but has enhanced certain aspects of that technique, Bohr said. However, he declined to specify exactly how the company did that.

Strained silicon results when a chipmaker applies a certain substance to the silicon transistor or substrate that reacts with the silicon atoms to either stretch or compress the channel, or the area through which electrons travel. This has the effect of increasing the drive current, improving transistor performance.

This improvement in performance means Intel can choose to run its chips faster than previous generations, or run them at the same speed using less power. The company has managed to produce 65-nanometer transistors that use higher drive currents but have the same amount of power leakage as the 90-nanometer transistors, Bohr said.

The additional metal interconnect layer improves performance and density, Bohr said. As chip companies put more and more transistors onto their chips, they need additional layers of interconnects to make sure those transistors can interoperate.

Intel insulated those interconnects with an improved version of the carbon-doped low-k dielectric used on the 90-nanometer process. Again, Bohr declined to specify exactly how the dielectric material was improved, but the dielectric material helps cut power leakage and reduce the capacitance of the interconnects.

Capacitance is a measure of how much electricity a circuit feature can store. By lowering the capacitance of the structures it uses in its circuits, Intel can reduce the power consumption.

Intel also reduced capacitance on the transistor gates, which are now 35 nanometers long. The smaller gates mean they can hold less electricity, but it also means that more power can leak through those tiny structures. Therefore, Intel kept the gate thickness constant from the 90-nanometer generation at only 1.2 nanometers to help prevent additional leakage from increased drive currents.

The Santa Clara company plans to introduce the sleep transistor in its static RAM (SRAM) cells that serve as the proving ground for the 65-nanometer process. A sleep transistor works somewhat like the power-saving techniques that Intel and other chip companies use to throttle power consumption in mobile processors when workload requirements change.

SRAM cells don’t need to access every portion of the cell at a given time, Bohr said. By putting unused transistors to sleep, or cutting the power flowing to those cells, Intel can reduce leakage and power consumption, he said.

Intel has already manufactured fully functional 70M bit SRAM chips that use all of the features described during the briefing, Bohr said.

The company has not said anything about what processors will mark the debut of the 65-nanometer process generation. The Prescott core for the Pentium 4 processor was Intel’s first 90-nanometer chip. It was launched in February of 2004, but began shipping to PC manufacturers in late 2003. It’s likely that the first 65-nanometer chip would follow the same pattern, but Intel would not comment on that possibility.