MIT researchers are looking into the tiny variations that can occur during chip fabrication that can have a big impact on the performance of processors powering high-speed communications gear. The researchers have developed a model that could help chip designers from the start of the process.
“We’re getting closer and closer to some of the limits on chip size, and variations are increasing in importance,” says Duane Boning, a professor of electrical engineering and computer science (EECS) and associate head of the department. “It’s becoming much more difficult to reduce variation in the manufacturing process, so we need to be able to deal with variation and compensate for it or correct it in the design.”
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