Direct wafer links reduce latency and networking hardware requirements, though enterprises may need a separate management stack alongside existing GPU infrastructure.
Cerebras Systems has unveiled the CS-4, a new rack-scale AI system that can connect its wafer-scale processors across racks without network switches, an approach designed to reduce communication latency as AI infrastructure grows more complex.
Cerebras, which competes with Nvidia and other AI accelerator suppliers, said the CS-4 can run up to twice as fast as its previous-generation CS-3.
In a test using the GPT-OSS-120B model, the company said it also delivered up to 30 times the per-user inference speed of GPU-based systems. Cerebras said actual throughput can vary depending on the model and serving configuration.
The CS-4 is the first system based on Cerebras’ new Nexus rack-scale architecture and includes Direct Wafer Links, which the company said can reduce wafer-to-wafer latency to as little as two microseconds.
The system also supports RoCE v2 over Ethernet, allowing it to connect with existing data-center networks. Cerebras said each CS-4 provides up to 7.2 Tbps of system I/O bandwidth.
For infrastructure teams, the more important question is what happens to the rest of the network when some of the switching between accelerators disappears.
Switchless links could cut complexity
Eliminating switches between Cerebras systems could reduce both infrastructure costs and power consumption, according to Neil Shah, vice president for research at Counterpoint Research.
“When you link wafer-scale chips directly rack-to-rack using Direct Wafer Links, you eliminate a huge, complex layer of networking hardware that typically eats up a big chunk of an AI cluster’s budget and up to a third of its electricity,” Shah said.
But the approach comes with a trade-off: point-to-point connections can offer less flexibility for rerouting traffic or handling failures than conventional switched fabrics.
The architecture could reduce dependence on traditional switching layers between Cerebras systems, but would not eliminate conventional networking requirements, said Manish Rawat, semiconductor analyst at TechInsights.
“External connectivity, storage, orchestration, and communication with heterogeneous compute will still require conventional networking,” Rawat said.
He said the bigger test is whether the architecture lowers infrastructure costs and makes production deployments easier to scale.
Data ingestion and cluster management would still rely on traditional Ethernet infrastructure, while external systems in disaggregated inference would communicate with the CS-4 over RoCE v2, said Danish Faruqui, CEO of Fab Economics.
RoCE support eases data-center integration
Cerebras has taken a standards-based approach to external connectivity, with RoCE v2 allowing the CS-4 to plug into existing high-speed Ethernet infrastructure.
Rawat said this could also make the system easier to use alongside other compute platforms, particularly in disaggregated inference deployments.
Inside the Cerebras fabric, the trade-off is different. Direct Wafer Links are proprietary, so third-party accelerators cannot be added to the fabric. Scaling it requires additional Cerebras systems, Shah said.
Faruqui said the operational divide may be more significant than the physical networking challenge. Existing orchestration environments are generally designed around conventional multi-accelerator nodes, while CS-4 relies on Cerebras’ own software stack to manage workloads across its internal wafer-scale fabric.
That could leave enterprises operating a separate management domain alongside their existing GPU infrastructure, he said.
“The key industry test will be whether customers see the architecture as an open component of a broader AI infrastructure or as a highly optimized but relatively proprietary stack,” Rawat said.
The proprietary model extends to software. Cerebras supports frameworks including PyTorch, but workloads run through the company’s CSoft software platform. Shah said the ecosystem lacks the maturity and breadth of Nvidia’s CUDA environment, which enterprises would have to weigh against the benefits of Cerebras’ wafer-scale approach.
Faster inference puts pressure elsewhere
Faster inference could put more pressure on storage and data-ingestion systems to keep the accelerators supplied with work.
“The challenge flips from the speed of token generation to the speed of feeding the input tokens and context data,” Shah said.
Faruqui said one pressure point could emerge during the prefill phase of inference, when a model processes the incoming prompt before generating tokens. In disaggregated deployments, that work may be handled outside the CS-4 and then transferred over Ethernet into the Cerebras system.
In that architecture, external network performance can become more important because model state and context data must be moved into the CS-4 quickly enough to keep the decoding engine busy, he said.
Power density remains a constraint
Cerebras is also positioning the CS-4 around power efficiency, saying it can deliver up to 10 times more throughput per watt than the CS-3.
Rawat said the efficiency gain could help as AI compute density rises but would not eliminate power and cooling constraints at scale. At the rack level, Faruqui said wafer-scale systems concentrate compute into a relatively small footprint, potentially placing greater demands on local power delivery and liquid cooling.
