* Measuring network performance - at the chip level
The most local of local-area networks is a network on a chip – at least that’s my reasoning for taking a very quick look at what’s called Network on Chip.
Network on Chip, or NoC, is an approach to designing chip architectures that is arising because of the sheer numbers of transistors that can be put on integrated circuits these days. Yes, Moore’s Law has come home to roost. Or something like that.
With Network on Chip, the chip is so complex that it is divided into regions. These regions consist of processing centers and related storage resources and so forth. The regions, or cores, are physically separate from one another, but they need to communicate via a switch fabric, hence the network.
As an illustration of where this is all going, Intel last month demonstrated an 80-core chip, the Teraflop Research Chip. The company at the time claimed the chip was “not much larger than the size of a finger nail while using less electricity than most of today’s home appliances.”
The latest news is that the Open Core Protocol International Partnership Association, or OCP-IP, announced an initiative toward open benchmarking of NoC environments. The industry group this week released a white paper (PDF) outlining the need for benchmarking everything from application modeling to performance evaluation to reliability.
The paper was developed by universities working on NoC research, including the University of British Columbia, Carnegie Melon University, the Royal Institute of Technology, Tampere University of Technology and Washington State University.
OCP-IP says later this year it will define a benchmark framework that would allow the NoC community to build a benchmarking suite.
