New server processor could handle trillions of calculations per second

The prototype of a revolutionary general-purpose computer processor, which has the potential of reaching trillions of calculations per second and handling massive applications, was unveiled by a team of computer scientists at The University of Texas at Austin today. The new processor, known as TRIPS (Tera-op, Reliable, Intelligently adaptive Processing System), could be used to accelerate industrial, consumer and scientific computing, the group said in a statement.  Each TRIPS chip contains two processing cores, each of which can issue 16 operations per cycle with up to 1,024 instructions in flight simultaneously. Current high-performance processors are typically designed to sustain a maximum execution rate of four operations per cycle. Though the prototype contains two 16-wide processors per chip, the research team aims to scale this up with further development. According to the group’s Web site, the TRIPS prototype chip is a 170 million transistor custom ASIC designed in a 130nm technology. The Austin TRIPS team partnered with IBM microelectronics for ASIC physical design, including placement, routing, and fabrication. The Defense Advanced Research Projects Agency (DARPA) is the primary sponsor of the group. Intel, Sun and the National Science Foundation are also contributors.   TRIPS is a demonstration of a new class of processing architectures called Explicit Data Graph Execution (EDGE). Unlike conventional architectures that process one instruction at a time, EDGE can process large blocks of information all at once and more efficiently, the group said.  Current multicore  processing technologies increase speed by adding more processors, which individually may not be any faster than previous processors. Adding processors shifts the burden of obtaining better performance to software programmers, who must assume the difficult task of rewriting their code to run well on a potentially large number of processors, the group said.  Professors Stephen Keckler, Doug Burger and Kathryn McKinley have been working on underlying technology that culminated in the TRIPS prototype for the past seven years. Their research team designed and built the hardware prototype chips and the software that runs on the chips. “EDGE technology offers an alternative approach when the race to multicore runs out of steam,” said Keckler, associate professor of computer sciences in a statement. Specific features of TRIPS include: ·          Key Technologies and Innovations·          Explicit Data Graph Execution (EDGE) instruction set architecture ·          Scalable and distributed processor core composed of replicated heterogeneous tiles ·          Non-uniform cache architecture and implementation ·          On-chip networks for operands and data traffic ·          Configurable on-chip memory system with capability to shift storage between cache·          and physical memory ·          Composable processors constructed by aggregating homogeneous processor tiles ·          Compiler algorithms and an implementation that create atomically executable blocks·          of code ·          Spatial instruction scheduling algorithms and implementation