New Efficient core design will excel at multithreaded applications like AI inferencing
The Hot Chips conference was the backdrop for Intel’s newest Xeon processor, the all-E-core codenamed Clearwater Forest and the first Xeon built on the company’s next-generation 18A process node.
Hot Chips is an annual conference that takes place every year on the campus of Stanford University, the alma mater of numerous Silicon Valley talents, including Pat Gelsinger and Jensen Huang. It is a deep dive in technology led by a slew of electrical engineers talking shop amongst themselves with no marketing people in sight.
Clearwater Forest is scheduled to ship in 2026 and will be one of the first built on the 18A manufacturing process, which is being used by Intel and its foundry business.
The processor packs 288 Efficiency cores and is the successor to the 144-core Sierra Forest chip currently on the market. In recent years, Intel has switched CPU design to Efficiency cores (E-cores) and Performance cores (P-cores). Their names are descriptors of what they are: E-cores are lower power and lower performance and designed for simple tasks, while P-cores are more complex, more powerful, and consume more power.
Most Xeon chips are all P-core, but this is different. While it’s an evolution of Intel’s Sierra Forest, it features a new core design for faster performance. Four cores share 4MB of L2 cache, and the chip doubles L2 bandwidth compared to the Sierra design. The chip will excel at multithreaded applications like AI inferencing, Intel stated.
There is also considerable reworking of the power subsystems, improving density and signaling efficiency. This combined with the 18A node process should help Intel close the performance gap that AMD has enjoyed so much with its more efficient designs.
That’s not to say that there won’t be considerable performance improvements as well. In a two-socket system, the chip will have 24 lanes of DDR5 8000 memory for 1.3Tb/s of memory bandwidth, 192 lanes of PCIe Gen 5 as well as 64 lanes of CXL connectivity, and 576 cores with 1152 MB of combined cache for 59 TF/s.
