Altera targets AI edge with updates for its Agilex FPGA portfolio

News
Oct 2, 20253 mins

Altera hardware and developer tools are launched as part of the company's newly established independence.

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Credit: evgeniy jamart / Shutterstock

Altera, the FPGA maker Intel acquired in 2015 and spun off earlier this year as an independent company, celebrated that independence with an update that includes a new product line and developer tools.

Altera is now 51% owned by Silver Lake Technology Management and 49% owned by Intel, and its products are manufactured by Intel, so “independent” is a relative term.

“The bigger picture of this independence helps us to operate with greater agility, faster decision making, so that we can adapt to our markets quickly and also bring the solutions in a way that it brings leadership to our customers who are trying to get those solutions into marketplace,” said Venkat Yadavalli, vice president and general manager of Altera in a press pre-briefing.

To celebrate this transition, Altera used its annual Innovator’s Day developer conference as the backdrop for the news, starting with the disclosure all Agilex FPGA families now in production, including Agilex 5 and Agilex 3 SoC FPGAs with integrated Arm subsystems for edge AI and hardware-software co-processing.

Next, its Agilex 5 D-Series has gotten a density boost of up to 2.5 times higher logic capacity and higher DSP ratios and bandwidth, powering edge AI inference, 4K/8K video, and 5G/6G use cases.

Memory interfaces have been significantly sped up, with support for DDR5 up to 5,600 MT/s and LPDDR5 up to 5,500 MT/s, for approximately 25% more throughput than prior specs.

The Agilex 5 line targets optimized performance for applications specifically targeting the embedded segments, such as industrial broadcast, video and vision, as well as other edge applications, said Yadavalli. “We are also planning to expand this this family of products even further to get into that edge compute,” he said.

 Agilex 3 is related to the low-end power and cost optimized product, which enables Altera to get into constrained applications where the size, weight and power become the primary vectors, he added.

On the software side, Quartus Prime v25.3 delivers faster compile times, lower resource use, and enhanced developer productivity. The new Quartus release includes early access to Visual Designer Studio, Altera’s 4th-generation system integration tool. Visual Designer Studio accelerates IP integration by automating the process of connecting IP blocks in the design flow. Altera claims Visual Designer Studio can slash the time it takes to get started on an FPGA design from five days to two hours when compared to using only RTL.

The full Agilex family is available now.

Andy Patrizio is a freelance journalist based in southern California who has covered the computer industry for 20 years and has built every x86 PC he’s ever owned, laptops not included.

Andy writes the Data Center Explorer blog for Network World. His work has appeared in a variety of publications, including Tom's Guide, Wired, Dr. Dobbs Journal, Tech Target, Business Insider, and Data Center Knowledge. Earlier in his career, he held editorial positions at IT publications like InternetNews, PC Week and InformationWeek.

Andy holds a BA in Journalism from the University of Rhode Island.

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