The 4.0 spec may not have much time in the market as a result
This is one of those stories that isn’t very sexy, but it is important. The PCI Express 3.0 data transfer standard has been around longer than it should have, and now it seems the PCI-SIG that develops the standard is making up for it with two new specs in two years.
The SIG—a consortium of 700 hardware vendors, including IBM, Intel and HP Enterprise—develops the spec, which is the standard for moving data around within a computer. Plug-in peripherals, like video cards and SSDs, use the PCI Express bus for data transfer.
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PCI Express 3.0, or PCIe, was finished in 2010, and motherboards began to appear in 2011. The 4.0 spec should have been done within three years but only now is being finished because if there’s one way to screw up development, it’s to have it done by committee, and 700 cooks can really spoil the broth.
Now the PCI-SIG has announced that PCIe 4.0 specification is finished, and it plans to have PCIe 5.0 ready to go by 2019, which is liable to cripple the 4.0 spec before it even gets out of the gate.
If 4.0 needs about a year to get rolling like 3.0 did (it takes motherboard vendors and card vendors time to develop and qualify their hardware), then the 4.0 spec is going to have about one or two years of time on the market. At that point, the Osborne Effect takes over and people will just wait.
“In our 25-year history, PCI-SIG has maintained its commitment to our rigorous specification development process, while delivering specifications that are in lock-step with industry requirements for high-performance I/O,” said Al Yanes, PCI-SIG chairman and president, in a statement. “PCIe 5.0 technology is the next evolution that will set the standard for speed, and we are confident that its 32GT/s bandwidth will surpass industry needs.”
The PCIe 4.0 architecture is geared toward power-efficient performance, with features such as extended tags and credits for service devices, reduced system latency, lane margining, superior RAS capabilities, scalability for added lanes and bandwidth, as well as improved I/O virtualization and platform integration.
The PCIe 4.0 specification has also been designed with key functional enhancements that future-proof the spec, which the SIG said will accelerate future specification development. And the 5.0 spec is going to be quite a boost in performance.
PCIe 5.0 will be four times faster than the current spec
PCIe 5.0 will offer 64GB/s of unidirectional transfer bandwidth, double that of 4.0, making it four times faster than the current spec and faster than DDR4 memory or even Nvidia’s high-speed NVLink technology. This means devices that use it, primarily GPUs and SSDs, will be able to move much more data much faster.
That’s important because buses tend to be the choke points in x86 architecture. It’s like an eight-lane highway suddenly dropping to two lanes. What’s that going to do to heavy traffic? Well, that’s what a GPU card goes through with the PCIe bus. The GPUs used in things such as AI and machine learning and supercomputing are all plugged into PCIe slots, and the fastest SSDs all use PCIe. So, a faster PCIe bus benefits everyone.
Data-intensive tasks with massive data sets such as big data, analytics, AI, and virtual reality will all benefit from this. Of course, it will take time for these products to enter the market and the data center. If the PCI-SIG hits its target goal of 2019 for standard finalization date, PCIe 5.0 could be in-market by 2020 or 2021. Then it takes time for old hardware to be replaced. That means 2021-22 at the earliest. By then, who knows what kinds of speed demon GPUs and SSDs we’ll be seeing.
