Xilinx joins others in releasing 65-nanometer chips

Xilinx released its first 65-nanometer chip this week, following a trend among semiconductor makers to keep pace with consumer demands by using more advanced production techniques.

Two requirements from users are forcing chip makers forward with their chip-production methods: They want ever-smaller, multiuse devices, which means companies have to shrink their chips even as they combine more functions onto each one. And users want the products at a reasonable price, which again requires more advanced production methods.

For Xilinx, the transition to smaller feature sizes on its Virtex chips, at just 65-nanometers, increased performance and reduced power consumption, the company said. The Virtex chips are a family of FPGA (field-programmable gate array) components, which can be programmed to perform a specific function. They are mainly used in networking gear. Most chips made today are ASICs (application-specific integrated circuits), which are created specifically for one device.

The nanometer measurement indicates the size of the transistors and other parts that are etched onto the chips. The more transistors, and the closer they are together, the faster the chip can perform tasks.

The U.S. chip designer joins an elite group by releasing its first 65-nanometer chip. So far only a few companies have made the leap to using 65-nanometer etching in mass production, including heavyweights Texas Instruments and Intel.

TI began sending working samples of a 65-nanometer wireless digital baseband processor to customers in March last year, and has increased production of the chips to volume levels.

Intel uses 65-nanometer technology in two of its manufacturing facilities in the United States, with two more due to come online this year, in Ireland and Oregon. The company has also developed chips using even tinier, 45-nanometer production processes, and is aiming for mass production at that feature size in 2007.

The companies are taking advantage of two chip technologies for the size innovations: larger silicon wafers and smaller etching techniques. With the silicon wafers, the issue is how they are made. The largest silicon wafers today are 12-inches in diameter and can produce more than twice as many chips as the older 8-inch wafers. A curious aspect of chip production is that silicon wafers are round and chips are square, meaning a lot of space is wasted on the edges of each wafer. They are round, because they are easiest to form that way, in cylindrical tubes, and then sliced like bread into individual wafers.

The wafer size also determines the cost of a factory, because each time the industry increases the size of wafers, the entire factory and production-line equipment usually has to be resized. It’s expensive. Building a 12-inch chip factory today can run about $3.6 billion, while an 8-inch plant would cost less than half that much.

Making the components on chips smaller is also tricky. Chips themselves come in various sizes, from the size of a thumb to smaller than the head of a nail. Chip firms make them smaller by shrinking the size of the transistors and gates on a chip. In recent years, some have even grumbled that current technologies are running into barriers and that new techniques will have to be found to shrink chip feature sizes.

Xilinx indicated that its 65-nanometer chips will be made by its contract manufacturing partners, Toshiba of Japan and Taiwan’s United Microelectronics Corp.

“I’m sure we can support all of their requirements,” said Alex Hinnawi, a spokesman for UMC in Taipei. The company operates two 12-inch factories, one in Taiwan capable of etching chips on 26,000 wafers per month, and another in Singapore with half that output.

UMC has manufactured 65-nanometer chips for two customers, including Xilinx, and is working with four additional customers on such products, Hinnawi said.

The company’s main rival in the contract chip-making business, Taiwan Semiconductor Manufacturing Co., has also been gathering orders for 65-nanometer technology. TSMC has delivered chips at that feature-size to customers for qualification, and listed five customers for 65-nanometer technology on a recent news release, including Broadcom Corp., Freescale Semiconductor and Altera Corp., which are all based in the United States.