Intel launches Agilex FPGA for smart networking

The new processor is built around processing network workloads to take the load off the CPU.

network traffic earth
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Intel has launched a field-programmable gate array—Agilex 7 with R-Tile—that features PCIe 5.0 and CXL capabilities for processing networking workloads.

The Agilex FPGA is primarily used in smartNICs that offload the processing of network traffic from the CPU, thus freeing up CPU capacity for other tasks. Intel sees Agilex playing a role in data centers, telecommunications, and financial services, among other high-traffic industries.

Agilex is an evolution of the old Stratix and Arria FPGA lines, and it’s designed to reflect changes in performance and features. Agilex 7 is the second most powerful FPGA family within the Agilex portfolio.

With this release, Agilex has undergone quite a change. The previous version was a PCI Express 4.0 product, built on a Stratix 10 DX design at 14nm. This new version supports PCI Express 5.0, and uses a chiplet design that breaks down the silicon into multiple smaller chips on the 7nm process.

With Intel’s chiplet approach, Agilex 7 with R-Tile combined with the F-Tile, which was announced earlier this year, offers 116Gbps of transceiver bandwidth, the fastest throughput yet among Intel FPGAs.

It also supports hard IP, which means functions like memory controllers and digital signal processors are hard coded into the silicon, rather than soft IP, which is programmed. The IP can’t be modified, but it also performs much faster and reduces design time for developing and deploying products.

The R-Tile is part of the new chiplet design where the chiplets are connected by a high-speed interconnect. R-Tile is a companion chip to the FPGA that specifically supports high-speed PCI Express connections and integrates with CPUs to accelerate high-performance computing workloads.

Agilex 7 supports CXL 1.1 and will support next generation CXL 2.0-capable CPUs when they ship. CXL is a high-speed interconnect that allows direct memory-to-memory communication for data sharing without having to go through CPUs and buses. Intel is saying that Agilex 7 builds now support CXL 1.1, and will support selected CLX 2.0 features pending validation, interoperability, and qualification with future CPUs.

Agilex 7 is shipping to OEM customers now.


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