Intel has unveiled a new packaging innovation for creating 3D chip packages and multiple chip connections ahead of the Semicon West conference in San Francisco this week.\nThe company is detailing its Embedded Multi-Die Interconnect Bridge (EMIB) technologies and Foveros 3D chip packages. This may sound like very inside baseball and best suited for the propellerhead crowd, but hear me out.\n\nChip packaging has always played a critical role in semiconductors, and it\u2019s getting more important as chipmakers such as Intel and AMD strain against the limits of Moore\u2019s Law. The chip\u2019s package is how the chip\u2019s electrical signals and power are routed.\nAs we move to 3D stacking, advanced packaging techniques allow for more complex semiconductor designs and break previous limits. 3D stacking has become standard in NAND flash, with chips packing up to 96 layers.\nCPU design is a little different. Even with process shrinks, chips are simply growing larger as more cores and more cache are added. This results in heat density and latency, as data has to be moved around the chip.\nAMD solves the problem, Intel plays catch-up\nAMD, once again taking the lead, solved this problem with its Epyc server chips. Rather than making a monolithic 32-core piece of silicon the size of a half dollar, it broke things up into four \u201cchiplets\u201d with eight cores each and connected by a very high-speed interconnect. This allowed for more cores while controlling heat and electronics.\nIntel did what it always does when AMD comes up with a new idea: It pooh-poohed it, then quietly adopted it (they did the same thing with multicore, 64-bit computing and on-CPU memory controllers). It is introducing what Intel calls co-EMIB. Co-EMIB, or Embedded Multi-die Interconnect Bridge, enables the connection of two or more Foveros (3D stacked chip) chiplets, just like Epyc.\nFoveros is already in production today in Intel\u2019s Stratix 10 field programmable gate arrays (FPGAs), 8th Gen Intel Core processors with Radeon Graphics, and Intel\u2019s forthcoming Lakefield hybrid CPU.\nHowever, Co-EMIB and Foveros is a short-term solution. Long-term, Intel is working on Omni-Directional Interconnect (ODI). ODI uses both horizontal plane communications like Co-EMIB but also something called Through-Silicon Vias (TSVs) for 3D stacking.\nIntel says TSVs offer lower resistance, which means more power, along with low latency, high-bandwidth paths between chips and the package substrate.\nThe problem with making TSVs is it\u2019s a monumentally expensive manufacturing process that can add 30% to the wafer cost, and Intel isn\u2019t going to eat that \u2014\u00a0customers are.\nThese are important support technologies that will help CPUs and FPGAs continue to make big leaps in performance, hopefully well beyond the 5-7% they\u2019ve been averaging. It means a significant redesign of chip architecture and manufacturing.\nAs more data-intensive applications such as artificial intelligence (AI), machine learning (ML), and analytics dominate the data center, the pressure is on to increase performance \u2014\u00a0and the massive, monolithic chip design clearly was reaching its limit. Co-EMIB and ODI represent new designs to address those limits and keep up performance.