Acquisitions and defections be damned, Arm Holdings is pushing forward with its Neoverse line of server processor designs with the launch of the Neoverse V1 and N2 processor architectures.\nThe new chips are the successors to the Neoverse N1 and E1 designs, which are used in server processors like Ampere\u2019s Altra, Amazon\u2019s Graviton2, and Marvel\u2019s ThunderX2. Arm claims these chips will deliver 40% to 50% better performance than the previous generation while consuming the same amount of power.\n\u201cThe emergence of Arm in the data center is being powered by many factors\u2014customization, efficiency, ecosystem diversity\u2014but all of that builds on top of performance,\u201d said Chris Bergey, senior vice president and general manager of Arm\u2019s infrastructure business, in a briefing with journalists and analysts. \u201cIf Neoverse wasn\u2019t delivering a significant measurable value proposition you would not see the market adoption and momentum that we are achieving,\u201d\nThe V1 architecture is for CPU workloads where single-threaded performance is paramount. The V1 adds scalable vector extensions (SVE), making it ideal for high-performance compute (HPC) and AI\/machine learning applications. V1 will also support bfloat16, PCIe 5.0 connectivity, DDR5, HBM2e and CCIX 1.0 for bidirectional coherent communications between chips across sockets and in-package chiplets.\nSVE enables execution of SIMD integer, bfloat16, or floating-point instructions on wider vector units using a software programming model agnostic to the width of the unit. In creating its HPC Arm processor, Fujitsu added its own SVE and got the top spot on the Top 500 supercomputer list for it.\nLike the N1, the N2 was built specifically for scale-out architectures. Arm is positioning it for SmartNICs, enterprise switches, and edge networks. It can support up to 192 cores, but it will run at 350 watts. That\u2019s GPU territory.\nN2 will be designed for 5nm process technologies, and those aren\u2019t even out yet. As such the N2 won\u2019t ship until next year, and that\u2019s to Arm licensees. They will then need time to make their own designs. Like V1, it will support PCIe 5.0 and DDR5, along with HBM3 as well as both CCIX 2.0 and CXL 2.0 for fabrics.\nArm also said it plans to make continued investments in technologies like Compute Express Link (CXL) and Cache Coherent Interconnect for Accelerators (CCIX) in order to enable ultra-low latency fabrics and desegregated computing platforms.