IBM readies Power5 microprocessor

IBM is readying the next version of the microprocessor that powers its pSeries and iSeries servers.

The company has prototypes running it its labs that have booted AIX, Linux and the OS/400 operating systems.

The Power5 will be used in IBM’s pSeries systems as soon as next year. When introduced, it will have a clock speed of slightly faster than 2 GHz and a small increase in memory cache size.

Its most important feature, however, will be symmetric multithreading, the notion that a single processor can act as a dual processor and improve the performance of applications by as much as 40%. The symmetric multithreading capability is similar to the hyperthreading Intel uses in its Xeon and Pentium 4 processors.

The Power5 chipsest will also use 130-nanometer technology. This will make chips that are only 130 billionths of a meter wide. In 2005, IBM expects to progress to 90-nanometer technology.

The company will also enhance the AIX operating system to allow multithreading to be turned off for transaction-intensive applications that run better on a single thread.

The chipset will generate less heat than previous versions.

Further, each memory core on the dual-core chipset will maintain its own L3 cache. While IBM declined to comment, the Power5 can also be divided into more partitions than the Power4 processor.

IBM introduced its first Power-based systems in 2001, and the company is not expected to swap them out for Intel Itaniums anytime soon. However, IBM will build a clustered server based on AMD’s 64-bit Opteron.

ASCI Purple, the supercomputer cluster being built at Lawrence Livermore National Laboratory, is expected to use as many as 12,544 Power5 processors. Operating at 100 teraflops, the ASCI Purple will be twice as fast as any supercomputer running today. ASCI Purple will be used to simulate America’s aging nuclear weapons stockpile without underground testing.

The Power5 will ship as part of IBM’s Enterprise Storage Subsystem, also known as Shark.