Roundup of high-speed networking updates from Intel, Marvell, Ranovus

Intel boosts bandwidth per channel in latest FPGA, Marvell unveils low-latency Teralynx 10 switch chip, and Ranovus previews co-packaged optics platform with AMD.

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The need for speed in the data center has never been greater, as data sets for AI and machine learning grow exponentially. Enterprises also need bandwidth to move increasingly large data sets, and security to protect data in transit. To that end, three vendors have announced new capabilities in the high-speed networking game. So, let’s run them down.

Intel launches Agilex 7 FPGAs with F-Tile

Intel has introduced its latest FPGA-based networking processor, the Agilex 7 with F-Tile. This PAM4 and NRZ dual-mode serial interface tile can deliver up to 116 Gbps and hardened 400 GbE intellectual property. This is double the bandwidth per channel of the previous generation of Intel FPGAs with reduced power consumption.

Agilex 7 offers customers the ability to create a custom chip design suited to their specific needs, since that is the nature of the FPGA. With its Hard IP blocks for 400G Ethernet and PCIe 4.0, it enables a range of Soft IP features, including GPON, HDMI, eCPRI, Fiber Channel, Interlaken, Display Port, and JESD204B/C.

With its 400 Gbps support and multiprotocol capabilities, Agilex provides up to 1.6 Tbps of optical networking, as well as applications such as 25/50G passive optical network for high-speed broadband applications. F-Tile also provides the scalability to implement new and next-generation applications, such as 5G mMIMO and passive optical networks (PON).

Marvell ships 51.2 Tbps switch chip

Marvell Technology has introduced Teralynx 10, a 51.2 Tbps programmable 5nm switch chip offering 800Gbps of throughput and design for massive network scale for AI and ML. A single Teralynx 10 replaces 12 of the 12.8 Tbps chips of the previous generation while offering 80% power reduction for equivalent capacity thanks to the reduction in the number of ports needed.

Teralynx 10 comes with what Marvell claims is the lowest latency of any programmable switch. In addition, Teralynx 10 supports congestion-aware routing and real-time streaming telemetry, so it can auto-tune network traffic if there is congestion on a port.

Switch system vendors using Teralynx 10 can develop a wide range of switch configurations, such as 32 x 1.6T, 64 x 800G, and 128 x 400G. It comes with features like IP forwarding, tunneling, rich QoS and RDMA as well as real-time network telemetry, including P4 in-band network telemetry (INT).

Teralynx 10 will sample in Q2.

Ranovus packages optics with AMD networking chip

Ranovus specializes in what it calls co-packaged optics (CPO) technology. It combines in a single package a processor chip with a PAM4 optical I/O for Ethernet switch, since fiber is much faster than copper wire. It has co-packaging deals with IBM, Intel, Broadcom, and Marvell and now AMD.

Ranovus announced interoperability of AMD Versal adaptive networking SoCs with its co-packaged Odin 800G direct-drive optical engine. This provides massive optical interconnect bandwidth for AMD’s SoC.

Hyperscalers especially are looking to move to 800 Gb connections for AI/ML workloads, but so are enterprises. CPO shows a lot of promise, because CPO drives the optics directly from the switch ASIC, enabling significant reductions in system power, footprint and cost per bit. 

Ranovus said availability of the AMD co-package chip is still two years away.


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